1. Field of the Invention
The invention relates to a semiconductor device, and more particularly, to a semiconductor device having asymmetrical patterns on a cell region of a substrate.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the FinFET can be controlled by adjusting the work function of the gate.
Typically, unit cell regions or cell regions containing multiple patterns such as gate patterns and contact plug patterns from FinFET devices are formed on semiconductor substrate, in which the patterns closest to the edges of the cell region are arranged symmetrically. For instance, the pattern closest to the left edge of the cell region is usually the same as the pattern closest to the right edge of the cell region. This design however often creates excessive empty regions between adjacent cell regions thereby affecting the profile of the device. Hence, how to improve this issue has become an important task in this field.